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AN1043
FIGURE 3:
INTERRUPT-ON-PIN-CHANGE EXAMPLE
Change cause interrupt.
Port state captured in
INTCAP
No affect on INT pin or
INTCAP
Change cause interrupt.
Port state captured in
INTCAP
GP3
Interrupt cleared and
INT
re-enabled
SPI
Given:
- GP3 configured to “interrupt-on-pin-change”
- INT pin configured for “active low”
Read INTCAP or GPIO
Read INTCAP or GPIO
FIGURE 4:
INTERRUPT-ON-CHANGE-FROM-DEFVAL EXAMPLE
GPINTEN – GPIO Interrupt-on-Change Enable Register
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
X
X
X
X
1
X
X
X
INTCON – Interrupt Control Register
IOC7
X
IOC6
X
IOC5
X
IOC4
X
IOC3
1
IOC2
X
IOC1
X
IOC0
X
DEFVAL – Default Value Register
DEF7
X
DEF6
X
DEF5
X
DEF4
X
DEF3
0
DEF2
X
DEF1
X
DEF0
X
Interrupt will occur if GP3 logic level = 1
Change cause interrupt.
Port state captured in
INTCAP
GP3 = DEF3
INT deactivates
GP3
INT remains
after SPI read
INT
SPI
DS01043A-page 4
No affect on INT
pin or INTCAP
Read INTCAP or GPIO
because GP3 = 1
(opposite of DEF3)
Read INTCAP or GPIO
? 2006 Microchip Technology Inc.
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